Design and Analysis of CMOS and Adiabatic 4-Bit Binary Multiplier

The power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high compatibility of VLSI systems used in various applications, the power dissipation in CMOS circuits arises from it’s switching activity ,which is influenced by the supply voltage and effective capacitance. The power dissipation can be reduced by adopting different design style. Adiabatic logic style is said to be an attractive solution for such low power electronic applications. The proposed technique has less power dissipation when compared to the conventional CMOS design style. This paper evaluates the 4-bit binary multiplier in different adiabatic logic style and their results were compared with conventional CMOS design. The simulation results indicates that the proposed technique is advantageous in many of low power digital applications. Keywords— Adiabatic logic, charge recovery, Low power, multiplier, Power supply INTRODUCTION The main objective of this thesis is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, this work focuses on the reduction of the power dissipation, which is showing an ever-increasing growth with the scaling down of the technologies. Various techniques at the different levels of the design process have been implemented to reduce the power dissipation at the circuit, architectural and system level. Furthermore, the number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. Then, to limit the power dissipation,Alternative solutions at each level of abstraction are proposed. The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this thesis work, a new CMOS logic family called ADIABATIC LOGIC, based on the adiabatic switching principle is presented. The term adiabatic comes from thermodynamics, used to describe a process in which there is no exchange of heat with the environment. The adiabatic logic structure dramatically reduces the power dissipation. The Adiabatic switching technique can achieve very low power Dissipation, but at the expense of circuit complexity. Adiabatic logic offers a way to reuse the energy stored in the load capacitors rather than the traditional way of discharging the load capacitors to the ground and wasting this energy. In this paper we present different multiplier designs based on adiabatic and conventional CMOS logic principle and their performance based on the power dissipation compared. The rest of the paper is organized as follows. Section 2 gives details of conventional charging and adiabatic charging principle, Section 3 explain different 4 bit multiplier implementations, Section 4 simulation results and finally Section 5 is conclusion. ADIABATIC PRINCIPLE The operation of adiabatic logic gate is divided in to two distinct stages: one stage is used for logic evaluation; the other stage is used to reset gate output logic value. Both the stages utilize adiabatic switching principle. In the following section conventional switching and adiabatic switching analyzed in detail. Conventional charging There are three major sources of power dissipation in digital CMOS circuits those are dynamic, short circuit and leakage power dissipation. The dominant component is dynamic power dissipation and is due to charging, discharging of load capacitance. The equivalent circuits of CMOS logic for charging and discharging is shown in Fig.1. The expression for total power dissipation is given by. Ptot=α.CL.V.VDD.fclk+ISC.VDD+Ile.VDD (1) Fig.1 Conventional CMOS a) Charging b) Discharging Eq.(1), the first term represents the dynamic power, where CL is the loading capacitance, fclk is the clock frequency, and α is the switching activity. In most cases, the voltage swing V is the same as the supply voltage Vdd, however, in some logic circuits, the voltage swing on some internal nodes may be slightly less. The second term is due to the direct-path short circuit current Isc which arises when both the NMOS and PMOS transistors are International Journal of Engineering Trends and Technology (IJETT) – Volume 7 Number 2 Jan 2014 ISSN: 2231-5381 http://www.ijettjournal.org Page 72 simultaneously active, conducting current directly from supply to ground. Finally, leakage current Ile which can arise from substrate injection and sub threshold effects is primarily determined by fabrication technology considerations. Adiabatic Switching Adiabatic switching can be achieved by ensuring that the potential across the switching devices is kept arbitrarily small. This can be achieved by charging the capacitor from a time varying voltage source or constant current source, as shown in Fig. 2. Here, R represents the on-resistance of the pMOS network. Also note that a constant charging current corresponds to a linear voltage ramp. Assuming that the capacitance voltage VC is zero initially, the variation of the voltage as a function of time can be found as Fig. 2 Schematic for adiabatic charging process